RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.

Joined July 2014
Only a few days left! Submit your proposals by Wednesday, Jan. 20 and join us at the #RISCV Pavilion at @58thDAC from Sunday, July 11 – Thursday, July 15 in San Francisco to showcase your RISC-V methods, design flows, and more. bddy.me/35MXgyL #58thDAC
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Curious to learn more about the lightweight, “scalar crypto”’ instructions that’ve been introduced to #RISCV? @notacademic and Markku-Juhani Saarinen will discuss this and more at the Real World Crypto Symposium tomorrow, Jan. 13 at 10:15 a.m. PT: bddy.me/2NczdTD
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Apple watch, step aside. I'm going to HAVE to go with the @ZeppGlobal #Zepp Z smartwatch that uses @risc_v! #opencollaboration #OpenSource
.@ZeppGlobal’s #Zepp Z smartwatch has a wearable chip based on #RISCV? With 90 sports modes, the Zepp Z is great for monitoring your health stats while you’re working out. Read about it here: bddy.me/2N32fol
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#LiveAlert Excited to interact with the VLSI Industry Expert? Here we have an excellent opportunity for you! Learn about @risc_v SoC, Job Opportunities, etc from Mr. Sivakumar P R, Founder & CEO, on Jan 28th at 6 PM. Register now for FREE, bit.ly/MSrisc
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Wir suchen Verstärkung für unser #Team bei @agra_uni_bremen: Wissenschaftliche/r Mitarbeiter/in (w/m/d) im Rahmen des #BMBF-Projektes #Scale4Edge uni-bremen.de/universitaet/d… #risc #riscv #Verifikation @risc_v @BMBF_Bund @UniBremen #jobs
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.@seeedstudio et @beagleboardorg mettent le calculateur monocarte @risc_v sous #Linux à moins de 150 dollars #BeagleV bit.ly/3ig9Yel
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